Abstract

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.